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| Wednesday, June 12, 2002, 10:30 AM - 12:00 PM | Room: Auditorium B
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SESSION 21
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| Equivalence Verification
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| Chair: Ziyad Hanna - Intel Corp., Haifa, ISR
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| Organizers: Shin-ichi Minato
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| Using an equivalence checker to prove the functional equivalence of two designs is a common and practical verification approach. In this session, new technologies are presented that enable extraction of complex circuits, allow sequential equivalence checking and handle hard-to-verify arithmetic operators.
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| 21.1 |
Automated Equivalence Checking of Switch Level Circuits
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|  | Speaker(s): | Tim McDougall - Motorola, Mawson Lakes, Australia
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|  | Author(s): | Atanas N. Parashkevov - Motorola, Mawson Lakes, Australia
Simon Jolly - Foursticks Pty Ltd, Frewville, Australia
Tim McDougall - Motorola, Mawson Lakes, Australia
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| 21.2 | A Practical and Efficient Method for Compare-Point Matching |
| Speaker(s): | Robert Damiano - Synopsys, Inc., Beaverton, OR
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| Author(s): | Demos Anastasakis - Synopsys, Inc., Hillsboro, OR
Robert Damiano - Synopsys, Inc., Hillsboro, OR
Hi-Keung T. Ma - Synopsys, Inc., Mountain View, CA
Ted Stanion - Synopsys, Inc., Hillsboro, OR
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| 21.3 | Self-Referential Verification of Gate-Level Implementations of Arithmetic Circuits |
| Speaker(s): | Ying Tsai Chang - Univ. of California, Goleta, CA
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| Author(s): | Ying Tsai Chang - Univ. of California, Goleta, CA
Kwang Ting (Tim) Cheng - Univ. of California, Santa Barbara, CA
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