Wednesday, June 12, 2002, 10:30 AM - 12:00 PM | Room: Auditorium B SESSION 21    Equivalence Verification    Chair: Ziyad Hanna - Intel Corp., Haifa, ISR    Organizers: Shin-ichi Minato    Using an equivalence checker to prove the functional equivalence of two designs is a common and practical verification approach. In this session, new technologies are presented that enable extraction of complex circuits, allow sequential equivalence checking and handle hard-to-verify arithmetic operators.      21.1 Automated Equivalence Checking of Switch Level Circuits    Speaker(s): Tim McDougall - Motorola, Mawson Lakes, Australia    Author(s): Atanas N. Parashkevov - Motorola, Mawson Lakes, Australia Simon Jolly - Foursticks Pty Ltd, Frewville, Australia Tim McDougall - Motorola, Mawson Lakes, Australia      21.2 A Practical and Efficient Method for Compare-Point Matching    Speaker(s): Robert Damiano - Synopsys, Inc., Beaverton, OR    Author(s): Demos Anastasakis - Synopsys, Inc., Hillsboro, OR Robert Damiano - Synopsys, Inc., Hillsboro, OR Hi-Keung T. Ma - Synopsys, Inc., Mountain View, CA Ted Stanion - Synopsys, Inc., Hillsboro, OR      21.3 Self-Referential Verification of Gate-Level Implementations of Arithmetic Circuits    Speaker(s): Ying Tsai Chang - Univ. of California, Goleta, CA    Author(s): Ying Tsai Chang - Univ. of California, Goleta, CA Kwang Ting (Tim) Cheng - Univ. of California, Santa Barbara, CA